The invention is based on a priority application DE 10064928.9, which is incorporated by reference herein.
The present invention relates to the field of telecommunications and computer technology and more particularly to a method of synchronizing at least one receiver module, a synchronizable receiver module therefor, and a clock generator module therefor.
In the telecommunications and computer technology sectors, the assemblies required for the operation of a device often cannot be arranged on one electronic board but must be distributed between a plurality of separate modules on one or more respective boards. In particular in telecommunications systems, redundant modules are also used as a safeguard against failure. For the modules to operate synchronously, the receiver modules receive a central clock signal which in the simplest case is only one clock pulse.
A central clock signal of this kind is generated for example by a central clock generator module and transmitted to the receiver modules. A clock channel of a bus to which the receiver modules are connected is provided for example for the transmission. The receiver modules then operate either directly with the clock signal tapped from the bus or for example synchronize their own local clock generator, provided on the respective receiver module, with the central clock signal.
In a consequently redundant system, a receiver module is however supplied not only with one clock signal but with at least one second clock signal, in which case the connected receiver modules select one of the clock signals as master synchronization signal for their synchronization and the other clock signal(s) serve as slave synchronization signals which are selected as clock signal(s) upon the failure of the master synchronization signal. Ideally all the clock signals are synchronous, the slave clock signals being synchronized for example with the master clock signals so that the receiver modules to be synchronized in principle can select any one of the clock signals as their respective master synchronization signal without any phase difference.
However, in high-precision network devices of telecommunications networks operating at a high clock frequency, for example in so-called cross-connects in SDH transmission technology (SDH=synchronous digital hierarchy), even very small phase shifts between the individual clock signals have a disturbing influence on the precision of the network device. The modules of a network device, which for example are I/O assemblies (I/O=input/output) or switching matrices, then no longer operate sufficiently in synchronism and messages passing through the modules of the network device are subject for example to data overtaking or overlaps.
The same problems arise even if, for reasons of redundancy, network devices in a telecommunications network are synchronized with more than one clock signal.
Therefore the object of the invention is to provide a method and device for a precise synchronization of at least one receiver module, in particular a receiver module in a telecommunications network or in a network device of a telecommunications network.
This object is achieved by a method of synchronizing at least one receiver module, in particular a receiver module in a telecommunications network or in a network device of a telecommunications network, which has the following steps: A first clock signal and a second clock signal are sent to the at least one receiver module. In addition, at least one item of master-slave-status information about the at least one first clock signal and/or the second clock signal is sent to the at least one receiver module. Based on the item of master-slave-status information, the at least one receiver module selects the first clock signal or the second clock signal as master synchronization signal for its synchronization.
The invention is based on the principle that the respective receiver module, which is sent at least one first clock signal and a second clock signal, and selects the at least one first clock signal or the second clock signal as master synchronization signal for its synchronization, is sent, in addition to the clock signals, an item of master-slave-status information about the clock signals, on the basis of which information the receiver module can determine which of the clock signals is currently the master clock signal and which clock signal is the slave clock signal. The receiver module then selects the clock signal identified as master synchronization signal for its synchronization and thus synchronizes itself with the clock signal operating with a higher degree of precision.
The invention can be used advantageously in any system with redundant clock distribution. The system can consist of one single device or for example a communications network. In a particularly preferred embodiment the invention is used in a transmission network, in particular a transmission network with a synchronous digital hierarchy (SDH) or in a network device of the transmission network, for example in a cross-connect of a SDH transmission network, a SONET network device (SONET=synchronous optical network) or a PDH network device (PDH=plesiosynchronous digital hierarchy). The receiver modules consist for example of input/output modules or switching matrix modules, which in all events require precise synchronization for smooth mutual cooperation.
Further advantageous developments of the invention are described in the dependent claims and in the description.
The master-slave-status information can in principle be sent to the receiver module(s) in addition to the respective clock signals as separate control information, for example on a separate data line.
The master-slave-status information can also be contained in the respective clock signals, at least partially so-to-speak as xe2x80x9cin-band-identifierxe2x80x9d. Here different variants are conceivable. For example a master/slave identifier, for example in the form of one bit, could be attached to the clock signals. Moreover, only that clock signal to which a master identifier is added could be characterised as master synchronization signal, while clock signals with no identifier are automatically regarded as slave clock signals. Additionally, only the slave clock signals, not however the master clock signal, could be identified.
Advantageously, one of the clock signals is defined as a preferred master synchronization signal. If it is then undetectable, on the basis of the item of master-slave-status information, as to which of the clock signals is to be selected as the master synchronization signal, for example because the master-slave-status information is not sent or is sent faultily to the respective receiver module or the master-slave-status information identifies more than one clock signal as master synchronization signal, the receiver module selects the clock signal defined as preferred master synchronization signal. Faults relating to the. master-slave-status information thus hardly affect the precision of the synchronization.
The clock signals are preferably generated by one or more clock generator module(s). These can for example each have their own clock generator, for example comprising an oscillator, and/or can regenerate a clock received from the exterior and distribute this among the receiver modules which they are assigned. The latter applies for example to SDH cross-connects, in the case of which input/output modules receive external clock signals at so-called I/O ports (I/O=input/output) respectively assigned to transmission paths. The clock generator modules preferably select the I/O port with the best clock quality as clock source and from the clock information thereof generate the redundant clock signals intended for the receiver modules.
The clock signals distributed by the clock generator modules are preferably synchronous with one another. For this purpose at least one first (master) clock generator module, which for example normally generates the clock signal serving as master synchronization signal, sends a second (slave) clock generator module synchronization signal from which the second clock generator module can detect the correct function of the first clock generator module. The two clock generator modules are supplied with a base clock signal, for example by the same I/O port, and thus run in synchronism.
If the second (slave) clock generator module no longer receives the synchronization signal and consequently the first clock generator module no longer operates correctly, the second (slave) clock generator module becomes the (master) clock generator module and preferably the clock signal generated by the second clock generator module then becomes the master synchronization signal.
In principle however it is also possible for the synchronization signal sent from the first clock generator module to the second not only to comprise a pure xe2x80x9csign of lifexe2x80x9d but also to contain information for the sychronization of the second clock generator module. For example, the clock signal generated by the first clock generator module could be sent to the second clock generator module for the synchronization thereof.
The clock signals preferably are sent to the receiver module(s) on separate clock lines assigned to the respective clock signals, so that for reasons of redundancy the clock signals are substantially independent of one another and disturbances in one clock signal do not affect the respective other clock signal. In principle, the clock signals could also be transmitted on a common line, for example using a suitable modulation process.
If they are not anyhow contained in the respective clock signals, the items of master-slave-status information assigned to the relevant clock signals are likewise preferably transmitted to the receiver modules on separate lines.
Expediently the clock signals contain items of source information from which the source of the clock signal, for example the clock generator module generating the clock signal, is detectable. Clock generator modules designated xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d insert these designations as source information, for example xe2x80x9cclock generator module Axe2x80x9d and xe2x80x9cclock generator module Bxe2x80x9d, into the respective clock signals. If a receiver module now receives a clock signal with the identifier xe2x80x9cclock generator module Axe2x80x9d on a clock line assigned to the clock generator module xe2x80x9cBxe2x80x9d, for example because a cable containing the clock line has been incorrectly plugged in, the receiver module can signal the error and optionally start an error management routine, for example internally change-over the clock lines assigned to the clock generator modules xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d. In principle it is sufficient in the case of two clock signals for only one of these to contain such an item of source information. Furthermore, the source information could also be contained in an item of control information assigned to the clock signals. For example, in a cable provided for the transmission of a clock signal, one line could be provided for the clock signal and for the source information and/or master-slave-status information.
In a preferred variant, the receiver module(s) are sent at least one third clock signal with which the receiver module(s) can perform a fine synchronization. For example, the master-and-slave synchronization signals serving for basic synchronization can be transmitted at a bit rate particularly suitable for measurement purposes, for example 2 Mbit/s, while the clock signal(s) serving for the fine synchronization can be transmitted at a different, higher clock frequency, for example the 2.43 MHz frequency typically used in the case of SDH, which however cannot be measured or can be measured only with difficulty when conventional measuring instruments are used.
In a particularly preferred variant of the invention it is taken into account that phase differences can occur between the clock signals received by a receiver module. These phase differences can be caused for example by unsynchronized or inadequately synchronized clock generator modules or by propagation time differences because the clock signals are transmitted to a respective receiver module on lines of different length. However, in the receiver module(s) there are provided delay means assigned to the clock signals, for example shift registers which can be dynamically scanned by means of multiplexers, with which the respective receiver module can correct any phase differences present between the clock signal serving as master synchronization signal and the clock signal(s) serving as slave synchronization signals, so that the receiver module can at any time switch-over without a phase jump between the clock signals made available by the delay means. Here it is particularly advantageous for the receiver module to delay the first selected clock signal, for example the clock signal selected as master synchronization signal, by a predetermined delay time which preferably corresponds to a maximum expected propagation time difference between the master clock signal and the slave clock signal(s). If for example the cables used for the transmission of the clock signals have a length of between 0 metres and at the maximum 200 metres, a signal propagation time on a 200 metre cable is set for example as predetermined delay time. The unselected clock signal, for example the respective slave clock signal(s), is/are likewise firstly delayed by the predetermined delay time. Then, however, the delay of the unselected clock signal is adapted so that finally all the clock signals at the outputs of the delay means are at least approximately in-phase.
For example, a shift register assigned to the unselected clock signal is scanned in stepped fashion at different memory locations adjustable by a multiplexer and the respective (unselected) clock signal is extracted. Then the phase difference between selected (master) clock signal and unselected (slave) clock signal is determined and the scanning setting of the multiplexer is adapted in order to reduce the phase difference.
The receiver module adapts itself automatically however to different phase differences between the clock signals, so that the receiver module can switch over between these with no phase jump and continues to operate in the event of the failure of a clock signal. In this way, taking the previously described example, cables of an any length up to 200 meters can be used for the transmission of the clock signals.
Obviously, the receiver modules and/or clock generator modules suitable to execute the method according to the invention can also be implemented as software modules, the program code of which can be executed by a suitable control means, for example a digital signal processor.